Semiconductor devices are used in a large number of electronic devices, such as computers, cell phones and others. One of the goals of the semiconductor industry is to continue shrinking the size and increasing the speed of individual devices. As devices shrink in size, the distance between devices also shrinks. One challenge is in processing adjacent devices so that process steps, such as doping, affects a target device, but not an adjacent device.
The shrinking of the critical dimension in semiconductor processes creates a tough challenge in the creation of a gate stack for complimentary metal oxide semiconductor (CMOS) transistors. In the creation of CMOS circuits, especially CMOS logic and memory circuits, it is common to have both n-channel MOS (NMOS) devices and p-channel MOS (PMOS) devices in close proximity to each other. Such a close proximity becomes especially challenging with respect to semiconductor processing.
In order to improve the performance of MOS devices, the gates of MOS devices are often implanted with a dopant to adjust the threshold, Vt. In a particular small geometry CMOS process, for example a 45 nm or a 65 nm process, the gates of NMOS devices can be doped prior to patterning, while the gates of PMOS devices remain undoped. A typical process implementation will mask the PMOS gate regions with a layer of resist prior to exposing the entire gate layer to an n+ ion implant. In small geometry processes, however, masking the PMOS regions is not entirely effective in preventing the ion implant from any doping of the PMOS gate regions. Because of the close proximity of NMOS gate regions to PMOS gate regions, n+ dopants can enter the PMOS gate region along the edge of the resist layer. Unintentional doping of the PMOS gate regions is disadvantageous because it can cause substantial Vt variation in PMOS devices. Such a Vt variation can cause performance problems including non-optimal circuit performance and device failures.
In the field of small, densely packed applications using small geometry transistors, what is needed is a method and structure that can selectively and precisely prevent regions of the semiconductor body from being doped during a semiconductor doping process.